A multicore-aware von Neumann programming model

An extension to the classic von Neumann paradigms is suggested, which -from the point of view of chip designers- considers modern many-core processors, and -from the point of view of programmers- still remains the classic von Neumann programming model. The work is based on the ideas that 1) the order in which the instructions (and/or code blocks) are executed does not matter, if some constraints do not force a special order of execution 2) a High Level Parallelism for code blocks (similar to Instruction Level Parallelism for instructions) can be introduced, allowing high-level out of order execution 3) discovering the possibilities for out of order execution can be done during compile time rather than runtime 4) the optimization possibilities discovered by the compile toolchain can be communicated to the processor in form of meta-information 5) the many computing resources (cores) can be assigned dynamically to machine instructions. It is shown that the multicore architectures could be transformed to a strongly enhanced single core processor. The key blocks of the proposal are a toolchain preparing the program code to run on many cores, a dispatch unit within the processor making effective use of the parallelized code, and also a much smarter communication method between the two key blocks is needed.