• DocumentCode
    3672957
  • Title

    From fan-out wafer to fan-out panel level packaging

  • Author

    T. Braun;K.-F. Becker;S. Raatz;V. Bader;J. Bauer;R. Aschenbrenner;S. Voges;T. Thomas;R. Kahle;K.-D. Lang

  • Author_Institution
    Fraunhofer Institute for Reliability and Microintegration, Berlin, Germany
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics for heterogeneous system integration. This paper describes the technological path from wafer level embedding to 24"×18" fan-out panel level packaging technology in combination with low cost PCB based RDL processes and discusses challenges and opportunities in detail. The technology described offers a cost effective packaging solution for various application as autonomous sensor nodes, packages for handheld consumer application or bio-medical application as sensor integration into microfluidics.
  • Keywords
    "Packaging","Application specific integrated circuits","Acceleration","Three-dimensional displays","Assembly","Compression molding","Microfluidics"
  • Publisher
    ieee
  • Conference_Titel
    Circuit Theory and Design (ECCTD), 2015 European Conference on
  • Type

    conf

  • DOI
    10.1109/ECCTD.2015.7300046
  • Filename
    7300046
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3672957