• DocumentCode
    3672996
  • Title

    Hardware property checker for run-time Hardware Trojan detection

  • Author

    Xuan Thuy Ngo;Jean-Luc Danger;Sylvain Guilley;Zakaria Najm;Olivier Emery

  • Author_Institution
    Institut MINES-TELECOM, TELECOM ParisTech, CNRS LTCI (UMR 5141), 75634 PARIS Cedex 13, France
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Nowadays, Hardware Trojans (HTs) become a real threat because of IC design and fabrication outsourcing trend. In the state of the art, many efforts were devoted to counter this threat, especially at netlist level. However, some clever HTs are actually a combination between a hardware and a software vulnerability, which, together, allow an exploitation. In this paper, we intend to detect such advanced HT, by resorting to a run-time detection. This method consists in identifying some high-level and critical behavioral invariants, and by checking them during the circuit operation. The assertion and Property Specification Language (PSL) is used to describe the properties to be checked. Then, a Hardware Property Checker (HPC) is created and integrated in the IC in order to verify these properties in runtime. We discuss how to define the critical properties for HPC. We also explain how this method is complementary with others, especially how the Hardware Checker can itself be protected against a tampering attempt. A case of study on LEON processor was performed to demonstrate the feasibility of this detection technique.
  • Keywords
    "Hardware","Trojan horses","Software","Registers","Field programmable gate arrays"
  • Publisher
    ieee
  • Conference_Titel
    Circuit Theory and Design (ECCTD), 2015 European Conference on
  • Type

    conf

  • DOI
    10.1109/ECCTD.2015.7300085
  • Filename
    7300085