Re-configurable coherent event forwarding mechanism for multiprocessor systems

End applications like automotive, mobile, industrial, communications and infrastructure require hardware architectures with multiple processing elements to reduce overall system cost and power. Typical hardware architectures consist of multiple processors to meet computational needs along with a rich set of peripherals to meet connectivity requirements. The complex interaction between the processing elements and the peripheral poses technical challenges in terms of assigning use case specific role for each component. Interrupts and events are one of the basic building blocks for communication, which typically gets statically assigned during design, prohibiting certain use cases. This paper proposes a simple and efficient architecture to route interrupts in multicore devices, which are fully configurable by software based on end-application. The solution consists of symmetric crossbar architecture to connect the processing elements to peripheral endpoints. The proposed architecture is optimal in terms of latency along with design and software efficiency. The proposed architecture is implemented in a multicore SoC (System-on-chip) catering to the automotive market. The implementation provides up to 420²⁰⁰⁰ combinations of possible interrupt connections, thereby enabling any possible use case. The proposed solution has no additional latency, one-time static configuration and adds a nominal overhead of 0.17% to the silicon die area.