Automatic generation of lightweight controllability and observability structures for analog circuits

In this paper a method is presented to address the automatic testing of analog ICs. Based on Design-for-Testability building blocks offering extra controllability and extra observability, a test infrastructure is generated for a targeted circuit. The selection of the extra blocks and their insertion into the circuit is done automaticaly by a proposed optimization algorithm. Adopting a defect-oriented methodology, this algorithm maximizes the fault coverage and minimizes the silicon area overhead. The proposed method is applied to an industrial circuit to generate an optimal test infrastructure combining controllability and observability. The case study shows that, with a silicon area overhead of less than 10%, a fault coverage of 91% can be reached.