Progress on quantum transport simulation using empirical pseudopotentials

After performing one-dimensional simulation of electron transport in narrow quantum wires without gate control in (Fang et al., 2014) and (Fu and Fischetti, 2013) using the open boundary-conditions full-band plane-wave transport formalism derived in (Fu, 2013), we now extend the work to simulate three-dimensionally field-effect transistors (FETs) with a gate bias applied and obtain their transport characteristics. We optimize multiple procedures for solving the quantum transport equation (QTE), such as using a selected eigenvalue solver, the fast Fourier transform (FFT), block assignment of matrices, a sparse matrix solver, and parallel computing techniques. With an expanded computing capability, we are able to simulate the transistors in the sub- 1 nm technology node as suggested by the ITRS, which features 5 nm physical gate length, 2 nm body thick6ness, 0.4 nm effective oxide thickness (EOT), 0.6 V power supply voltage, and a multi-gate structure. Here we simulate an armchair graphene nanoribbon (aGNR) FET using a gateall- around architecture and obtain its transport properties. We will discuss the numerics concerning the matrix size of the transport equation, memory consumption, and simulation time.