An Analytic Approach on End-to-End Packet Error Rate Estimation for Network-on-Chip

Network-on-Chip (NoC) are well-established for scalable on-chip communication, but technology generations of 22~nm and below, as well as aggressive voltage scaling to reduce NoC power consumption, introduce new variability challenges resulting in errors on wires and registers. Based on the probabilities of single bit flips, this paper focuses on the expected end-to-end packet error probabilities in NoC. We investigate the influence of individual bit error probabilities, the number of hops between communication partners, as well as the packet size. To evaluate these parameters, we propose an analytic approach which abstracts technology details of NoC data transport entities, such as links and buffers, and models each entity as a binary symmetric channel (BSC). The proposed probabilistic approach obtains equations for system-level NoC reliability estimates which allow an evaluation without the necessity to deploy time-consuming simulations.