An implementation architecture design of LU decomposition in resource-limited system

LU decomposition is a key kernel of computation in liner algebra and various engineering applications. In this paper, based on the platform of FPGA, we proposed a novel architecture to accelerate the computation. The processing element (PE) is reused via pipeline technology, which makes our design more resource-efficient and available to applications with limited hardware resources and real-time requirement. Our design works at 73.5MHZ, achieves a fairly good acceleration ratio considering the application scenarios and the resources consumed. The design can be easily expanded to play a role in higher dimension matrix factorization situation.