STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance

The series resistance of STT-MRAM cells becomes increasingly important in deeply scaled nodes. Next to the typical scaling of width and thickness of the copper layers, barriers further reduce the cross-section of the actual copper. Moreover, at these small sizes, the resistivity of copper degrades compared to bulk copper. This paper presents a novel STT-MRAM cell design with partial source line planes, which improves the tradeoff between area and source line resistance. A single source line is shared among multiple bit line rows of the embedded memory array, resulting in a smaller cell area at the same source line resistance or a reduced resistance at the same area. The design with a partial source line plane shared among 4 bit line rows results in an area reduction of 11% at the same source line resistance. Alternatively, at the same area, the source line resistance is reduced by more than a factor of 4. The reduced series resistance of the cell results in a performance gain and a reduction of energy consumption.