Conservatively Analyzing Transient Faults

Due to the decreasing size of transistors, the probability of transient errors and the variability of the transistor´s characteristics in electrical circuits are continuously increasing. These issues demand for techniques to check the robustness of circuits and their behavior under transient faults and variability. We present a conservative algorithm to decide if a transient fault leads to erroneous output of a circuit. Our approach considers logical, timing, and electrical masking as well as variability in the gates. In experiments, we show the runtime of our implementation on the ISCAS-85 benchmarks and compare our approach to precise transistor-level simulations as well as fast logic level analysis.