Hybrid STT/CMOS Design of an Interrupt Based Instant On/Off Mechanism for Low-Power SoC

This paper describes the design and the evaluation of a low-power System-on-Chip (SoC) in an advanced hybrid 40nm magnetic/CMOS technology node. Without external memory interface, the processor of the SoC benefits from a privileged access to the embedded NVM (Non-Volatile Memory), providing means for internal data storage and integrity thanks to its inherent non-volatility. Furthermore, a method based on an IRQ (Interrupt Request) controls the instant-on/off features of the SoC at assembler level through the use of NVM elements and improves the whole system in terms of power consumption and functionality enhancements, compared to an equivalent system relying on standard volatile memory blocks only. We discuss our simulation results on the basis of still image compression benchmarks at various data throughputs and show the benefits of NVM even for rather computation intensive algorithms.