TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning

Three-dimensional (3D) Network-on-Chip (NoC) based designs can utilize communication in vertical dimension to reduce distance between cores. Vertical connections are best implemented using Through-Silicon-Via (TSV). However, TSV geometry restricts the number of 3D routers in any layer of the die. This work proposes a strategy to select the TSV positions. This has been augmented by developing a core mapping procedure based on the Kernighan-Lin graph bi-partitioning algorithm, improved via an iterative improvement phase. The overall approach shows promising results compared to the existing mapping and TSV placement algorithms.