A high-efficiency high energy density buffer architecture for power pulsation decoupling in grid-interfaced converters

A high-efficiency high-energy-density buffer architecture is proposed for power pulsation decoupling in power conversion between DC and single phase AC. We present an active decoupling solution that yields improved efficiency and reduced circuit complexity compared to existing solutions. By connecting a buffer converter in series with the main decoupling capacitor, the main capacitor is allowed larger ripple for improved energy utilization (and thus much reduced volume), while the DC bus voltage is maintain close to ripple free. The buffer converter has low voltage stress and is only processing a small fraction of the total power of the entire architecture, allowing a very small active circuit volume and very high system efficiency. A control scheme is proposed to exploit the small remaining bus ripple to compensate the power loss in the power converter and balance the power cycle of the buffer architecture. A 2 kW hardware prototype has been built to demonstrate the benefit of the proposed solution. The hardware prototype achieves 20 times capacitance reduction and 2 times overall volume reduction compared to the conventional passive decoupling solution. An energy density of 110 W/inch³ and an efficiency above 98.7% across a wide load range has been experimentally verified.