Title :
3D integration ESD protection design and analysis
Author :
Souvick Mitra;Ephrem Gebreselasie; You Li;Robert Gauthier;Joel Silberman;Christy Tyberg;Katsuyuki Sakuma; Thuy Tran-Quinn;Koushik Ramachandran;Matthew Angyal
Author_Institution :
IBM Microelectronics Semiconductor Research and Development Center, Essex Junction, VT 05452, USA
Abstract :
A Design of Experiments (DOEs) matrix was created to evaluate probability of fails during a complex 3D integration process as a function of ESD protection level. A detailed set of pass/fail criteria based on circuit performance was established. Based on measured samples, functionality test and leakage test show circuit performance degradation and larger fail rate after chip bonding on designs without ESD protection.
Keywords :
"Electrostatic discharges","Three-dimensional displays","Topology","Bonding","Semiconductor device measurement","Testing","Receivers"
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2015 37th
DOI :
10.1109/EOSESD.2015.7314791
