A 0.5-V multi-channel low-noise readout front-end for portable EEG acquisition

This article presents a low-noise readout front-end suitable for Electroencephalogram (EEG) acquisition. The chip includes 8-channel fully-differential instrumentation amplifiers, utilizing chopper stabilization technique for reducing the flicker noise, each amplifier with a small G_m-C low-pass filter, a programmable gain amplifier, and a 10-bit successive approximation register (SAR) ADC with a detect logic for DAC switching. The chip is fabricated with the TSMC 90nm CMOS process. The low-noise readout front-end has simulated frequency response from 0.57 Hz to 213 Hz, programmable gain from 54.4 dB to 87.6 dB, integrated input-referred noise of 0.358 μVrms within EEG bandwidth, a noise efficiency factor (NEF) of 2.43, and a power efficiency factor (PEF) of 2.95. The overall system consumes 32.08 μW under 0.5-V supply.