• DocumentCode
    3687455
  • Title

    Cross coupled digital NAND gate comparator based flash ADC

  • Author

    Parag P. Kute;Pravin Dakhole;Prachi Palsodkar

  • Author_Institution
    Yeshwantrao Chavan College of Engineering, Hingna Rode, Wanadongari, Nagpur, Maharashtra 441110, India
  • fYear
    2015
  • fDate
    4/1/2015 12:00:00 AM
  • Firstpage
    1718
  • Lastpage
    1721
  • Abstract
    This paper demonstrates the Flash ADC which is constructed using digital 3-input cross coupled NAND gates. These cross coupled configuration of NAND gates form a comparator of flash ADC. It is latch comparator which operates on single phase clock Φ. The output of comparator is thermometer code. An encoder is constructed that encodes the thermometer code to binary as output of comparator. The design is simulated in 180nm technology and implement 4 bit flash ADC version. The Flash ADC is designed in TANNER S-EDIT 13.0.
  • Keywords
    "Logic gates","Latches","Clocks","Decoding"
  • Publisher
    ieee
  • Conference_Titel
    Communications and Signal Processing (ICCSP), 2015 International Conference on
  • Type

    conf

  • DOI
    10.1109/ICCSP.2015.7322814
  • Filename
    7322814