• DocumentCode
    3689017
  • Title

    Vertical field effect transistor with sub-15nm gate-all-around on Si nanowire array

  • Author

    G. Larrieu;Y. Guerfi;X.L Han;N. Clément

  • Author_Institution
    LAAS CNRS 7 Avenue colonel Roche, 31077 Toulouse, France
  • fYear
    2015
  • Firstpage
    202
  • Lastpage
    205
  • Abstract
    A vertical MOS architecture implemented on Si nanowire (NW) array with a scaled Gate-All-Around (14nm) and symmetrical diffusive S/D contacts is presented with noteworthy demonstrations both in processing (layer engineering at nanoscale), in electrical properties (high electrostatic control, low defect level, multi-Vt platform) in the fabrication of CMOS inverters and in the perspective of ultimate scaling.
  • Keywords
    Decision support systems
  • Publisher
    ieee
  • Conference_Titel
    Solid State Device Research Conference (ESSDERC), 2015 45th European
  • ISSN
    1930-8876
  • Print_ISBN
    978-1-4673-7133-9
  • Electronic_ISBN
    2378-6558
  • Type

    conf

  • DOI
    10.1109/ESSDERC.2015.7324750
  • Filename
    7324750
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3689017