DocumentCode :
3689823
Title :
Modeling and analysis of vertical noise coupling between clock tree and channel routing wire in 3D mixed signal integration
Author :
Shiwei Wang;Yingtao Ding;Huanyu He;Jian-Qiang Lu
Author_Institution :
Department of Electronic Science and Technology, Beijing Institute of Technology, Beijing, China
fYear :
2015
fDate :
5/1/2015 12:00:00 AM
Firstpage :
79
Lastpage :
82
Abstract :
This paper reports on the vertical noise coupling between a clock wire in digital IC and channel routing wires in analog IC in 3D mixed signal integration. Full wave electromagnetic simulations are employed to evaluate the vertical noise coupling. The coupling mechanism is discussed with transfer impedance. Insights to vertical noise coupling between interconnects in 3D integration are offered and possible solutions are provided to reduce the noise.
Keywords :
"Couplings","Three-dimensional displays","Wires","Clocks","Routing","Integrated circuit modeling"
Publisher :
ieee
Conference_Titel :
Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM), 2015 IEEE International
ISSN :
2380-632X
Electronic_ISBN :
2380-6338
Type :
conf
DOI :
10.1109/IITC-MAM.2015.7325631
Filename :
7325631
Link To Document :
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