3D Shared Bus Architecture Using Inductive Coupling Interconnect

Attention has been focused on 3D chip stacking for reducing the semiconductor area per chip while maintaining the overall performance. By using inductive coupling wireless Thru-Chip Interface (TCI) in chip stack for a 3D multiprocessor, the replacement/addition/removing of chips is made possible using the inductive coupling wireless TCI in the chip stack for a 3D multiprocessor and thus, high flexibility is provided. A bus can be easily formed with the TCI by stacking duplex wired coils in the same place on the stacked chip. However, traditional static time division multiple access (STDMA) cannot make use of the potential bus bandwidth, while dynamic time division multiple access (DTDMA) requires a lot of coils that cannot be efficiently used for the control signals. We propose an asynchronous TDMA bus (A-TDMA bus) that uses the CSMA/CD protocol and a resonant synchronous TDMA bus (RS-TDMA bus) that uses a resonant synchronized clock and a look-ahead technique to improve the use of the bandwidth of a 3D shared bus. The results of a network simulation using the GEM5 simulator showed that the zero-load latency of both proposed methods was reduced by 29% in a four-chip stack and 50% in an eight-chip stack compared to that of STDMA. A full system simulation using GEM5 shows that the execution time of the proposed methods decreased by 6.5% in the four-chip stack and 17% in the eight-chip stack compared with that of STDMA.