On real-time implementaion of 400 Gbps dual polarization 16-QAM coherent intradyne receiver

This paper describes a real time hardware implementation of an adaptive fractionally spaced feed forward equalizer (FFE) on FPGA technology as preliminary step toward the development on a semi-custom ASIC 28 nm. The presented equalizer is a part of a digital signal processing (DSP) system designed to be applied in a 400 Gbps dual polarization optical intradyne coherent system using 16-QAM modulation format. The whole DSP system is composed of the Automatic Frequency control (AFC) module, Bulk dispersion compensation module, FFE and a symbol-by-symbol detector. FFE is devoted to the compensation of linear effects due to the propagation along the fiber as group velocity dispersion (GVD) and polarization mode dispersion (PMD). The proposed solution for equalizer implementation has been ad hoc designed and optimized in order to minimize hardware occupancy. This architecture allows to reduce the number of look-up tables (LUTs) of more than 40% respect to standard implementation, reaching a minimum value of 2.052.864 LUTs corresponding approximately to one FPGA.