CMOS implementation of static threshold gates with hysteresis: A new approach

This paper develops a new approach to design static threshold gates with hysteresis, based on integrating each pair of pull-up and pull-down transistor networks into one composite transistor network. The new static gates are then compared to the original ones in terms of delay, area, and energy consumption. In order to compare the new gate style with the original one at the circuit level, a delay-insensitive NULL Convention Logic (NCL) 4×4 pipelined multiplier is developed and simulated with each gate style. The results show that the new gate style offers 27% speed-up with only a 5% increase in area and almost the same energy consumption.