DocumentCode :
3694092
Title :
ArchFP: Rapid prototyping of pre-RTL floorplans
Author :
Gregory G. Faust;Runjie Zhang;Kevin Skadron;Mircea R. Stan;Brett H. Meyer
Author_Institution :
Department of Computer Science, University of Virginia, Charlottesville, USA
fYear :
2012
Firstpage :
183
Lastpage :
188
Abstract :
There has been a fundamental shift from ever more complex single cores to single chip multi-core (CMP) designs. Along with this opportunity come major challenges; notably the sheer size of the CMP design space. An integrated suite of tools is needed that provides life-cycle support from early prototyping to final design. Here we present ArchFP, a floorplanning tool targeted towards prototyping of pre-RTL CMP design concepts. As such, it is complementary to traditional floorplanners that are more appropriate later in the design cycle.
Keywords :
"Geology","Artificial intelligence","Layout","Switches","Joints"
Publisher :
ieee
Conference_Titel :
VLSI and System-on-Chip, 2012 (VLSI-SoC), IEEE/IFIP 20th International Conference on
Print_ISBN :
978-1-4673-2658-2
Type :
conf
DOI :
10.1109/VLSI-SoC.2012.7332098
Filename :
7332098
Link To Document :
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