Reliability enhancement of power gating transistor under time dependent dielectric breakdown

As the technology shrinks to nano-scale, CMOS transistors pose more challenges to circuit design. One of the reliability challenges is time dependant dielectric breakdown. Scaling of the gate oxide increases the chance of dielectric breakdown due to presences of impurities in the oxide. Dielectric breakdown has a progressive nature resulting in gate current increase over time leading to a permanent short circuit. Power gating is an effective method for leakage power reduction. In a power gated circuit, the power gating transistor is the biggest transistor with the highest stress probability. Hence, the power gating transistor has the highest change of dielectric breakdown. A breakdown detection and repair method is proposed to enhance the reliability of power gating in nano-scale by optimally introducing sleep transistor redundancy. The proposed design is lower power and is immune against breakdown. A modeling and optimization framework is also proposed to optimize the trade-off between area overhead and overall breakdown probability. The results of implementation in a predictive 32nm technology shows that with an area constraint of 2% overhead for a benchmark circuit, the failure probability is reduced to 7.5e-18 and with the constraint of le-6 failure probability, the area overhead is 1.3% of the area of the benchmark circuit.