Title :
A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm
Author :
Jaspal Singh Shah;David Nairn;Manoj Sachdev
Author_Institution :
Department of Electrical and Computer Engineering, University of Waterloo, 200 University Avenue West, Ontario N2L 3G1 CANADA
Abstract :
An eight transistor static random access memory cell with an access transistor-less architecture is presented that shows high soft error robustness and low leakage current. A 32kb memory array is designed in 65 nm CMOS process. The cell provides 5.6x better immunity to soft errors when compared to a conventional SRAM cell. The cell shows 9.4x smaller read current than a 6T SRAM cell. The featured cell also shows read and write margin improvements.
Keywords :
"Computer architecture","Microprocessors","Robustness","MOSFET","SRAM cells"
Conference_Titel :
VLSI and System-on-Chip, 2012 (VLSI-SoC), IEEE/IFIP 20th International Conference on
Print_ISBN :
978-1-4673-2658-2
DOI :
10.1109/VLSI-SoC.2012.7332116
