• DocumentCode
    3694824
  • Title

    ESD protection design with latchup-free immunity in 120V SOI process

  • Author

    Yi-Jie Huang;Ming-Dou Ker;Yeh-Jen Huang;Chun-Chien Tsai;Yeh-Ning Jou;Geeng-Lih Lin

  • Author_Institution
    Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    Electrostatic discharge (ESD) protection with low-voltage (LV) field-oxide devices in stacked configuration are proposed for high-voltage (HV) applications in a 0.5-μm 120V SOI process. Stacked LV field-oxide devices with different stacking numbers have been verified in silicon chip to exhibit both of high ESD robustness and latchup-free immunity for HV applications.
  • Keywords
    "Electrostatic discharges","Stacking","Robustness","Layout","Thyristors","Silicon","Breakdown voltage"
  • Publisher
    ieee
  • Conference_Titel
    SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE
  • Type

    conf

  • DOI
    10.1109/S3S.2015.7333481
  • Filename
    7333481
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3694824