DocumentCode :
3694845
Title :
Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing
Author :
Takahiro Hanyu;Masanori Natsui;Daisuke Suzuki;Akira Mochizuki;Naoya Onizawa;Shoji Ikeda;Tetsuo Endoh;Hideo Ohno
Author_Institution :
Laboratory for Brainware Systems, Research Institute of Electrical Communication, Tohoku University, Japan
fYear :
2015
Firstpage :
1
Lastpage :
3
Abstract :
Novel logic-LSI architecture, “nonvolatile logic-in-memory (NV-LIM) architecture,” where nonvolatile storage elements are distributed over a logic-circuit plane, is proposed as a promising candidate to overcome performance wall and power wall due to the present CMOS-only-based logic LSIs. Some concrete design examples based on the NV-LIM architecture are demonstrated and their usefulness is discussed in comparison with the corresponding CMOS-only-based realization.
Keywords :
Decision support systems
Publisher :
ieee
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE
Type :
conf
DOI :
10.1109/S3S.2015.7333502
Filename :
7333502
Link To Document :
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