DocumentCode :
3694847
Title :
Technology scaling: The CoolCubeTM paradigm
Author :
F. Clermidy;O. Billoint;H. Sarhan;S. Thuries
Author_Institution :
Univ. Grenoble Alpes, F-38000 Grenoble, France, CEA, LETI, MINATEC Campus, F-38054 Grenoble, France
fYear :
2015
Firstpage :
1
Lastpage :
4
Abstract :
Scaling race towards aggressive nodes is getting more and more difficult as dimensions are getting close to the atoms ones. New solutions have to be investigated to find new ways of scaling while keeping the Moore´s law benefits in terms of area, power, performance and cost. These solutions should leverage on existing technologies for reducing their development cost by proposing new usages. Also, as cost of designing complex systems explodes, these new technologies should come with design techniques close to existing ones without increasing their complexity. Finally, current technological issues such as increased complexity of Back-End-Of-Line (BEOL) with the successive delays of Extreme-Ultra-Violet lithography should be solved. This multi-dimensional problem makes candidates difficult to emerge. The sequential 3D CoolCubeTM technology is one of them: bringing very fine pitch 3D interconnects and leveraging on existing technologies, it´s opening the door to real 3D-VLSI with the hope of reducing the actual pressure on BEOL while providing real 3D routing possibilities. However, many roadblock in terms of design still exist. In this paper, we show three aspects of design methodology showing its growing maturity and a PPA analysis based on this methodology showing that gains can meet the classical scaling requirements.
Keywords :
"Three-dimensional displays","Standards","Routing","Tungsten","Wires","Complexity theory","Logic gates"
Publisher :
ieee
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015 IEEE
Type :
conf
DOI :
10.1109/S3S.2015.7333504
Filename :
7333504
Link To Document :
بازگشت