Impact of technology and voltage scaling on LEON3 processor performance and energy

Although CMOS technology scaling has proceeded to sub-20nm nodes, FinFET devices are considered as the technology-of-choice for sub-20nm technology nodes due to the improved gate control [1]. On the other hand, voltage scaling provides us an energy efficient solution to the VLSI design, such as the near-threshold computing technique [2]. This work investigates the performance and energy consumption of LEON3 processor under technology and voltage scaling. Specifically, in order to study the impact of technology and voltage scaling, this work (i) develops 7nm gate length FinFET, ITRS 7nm FinFET (with 11nm actual gate length), ITRS 16nm CMOS, and ITRS 22nm CMOS Verilog-A device models using Synopsys TCAD tools [3], (ii) builds up the standard cell libraries using the developed Verilog-A models for the four previously mentioned technology nodes under a set of different supply voltage levels (i.e., from near-threshold to super-threshold), and (iii) synthesizes LEON3 processor (datapath plus L1 and L2 caches) using the developed standard cell libraries to compare the impact of technology and voltage scaling on the performance and energy consumption of LEON3 processor.