Proposed static timing analysis framework for extracted 3D integrated circuits (3D-STA)

3D integration of digital designs presents an important paradigm shift that introduces several benefits in speed, power, area, and footprint. Significant work has been done so far to enable CAD tools to handle 3D designs and account for TSVs. Yet, it is not as mainstream as conventional planar CAD tools. This work explores enabling existing flow and tools to handle full 3D designs without introducing drastic changes or excessive computations. It focuses on full 3D design STA with routing parasitics for its critical importance in the digital design flow. It proposes and implements an STA framework that efficiently handles full 3D extracted digital designs, as well as, regular planar ones. It presents details on the TSV extraction model, connectivity representation, and delay calculations. The framework can be easily adapted for placement and routing optimizations as well.