On-chip Delay Line for Extraction of Decorrelated Phase Noise in FMCW Radar Transceiver MMICs

Estimation of phase noise (PN) has become economically feasible for integration in many of today´s semiconductors. Several contributions propose concepts that obtain a good estimate of the PN´s power spectrum without even requiring a reference oscillator. Differently, in this work we aim to estimate the time domain representation of the residual PN in the intermediate frequency domain of a frequency modulated continuous wave (FMCW) radar transceiver. For that, an artificial on-chip target is utilized, which is to be incorporated into an existing monolithic microwave integrated circuit (MMIC). The estimated decorrelated phase noise is required for cancelation of short-range leakage originating from an unwanted signal reflection superimposing the overall channel response of the radar. We determine the minimum required delay such that the residual PN of the on-chip target exceeds the intrinsic noise. Further, three different realizations of the delay line in the MMIC are compared. We verify our analytical derivations with a full FMCW radar system simulation.