Traffic-Aware Application Mapping for Network-on-Chip Based Multiprocessor System-on-Chip

Network on Chip (NoC) has become a promising solution for the communication paradigm of the next-generation multiprocessor system-on-chip (MPSoC). As communication has become an integral part of on-chip computing, researchers are paying more attention to its implementation and optimization. Traditional techniques that model inter-processor communication inaccurately will lead to unexpected runtime performance, which is on average 90.8% worse than the predicted results based on an observation. In this paper, we present an application mapping and scheduling technique for NoC-based MPSoCs that integrates fine-grain optimization on inter-processor communications with the objective of minimizing the schedule length. A communication model is proposed to address properly the latency of inter-processor communication with network contention. Performance evaluation results show that solutions obtained by the proposed technique can generate realistic performance that is on average 34.7% higher than traditional techniques, and the Integer-Linear Programming (ILP) based approach can outperform the state-of-the-art heuristic algorithms by 31.1%. A case study on H.264 HDTV decoder shows that our approach achieves 22.8% improvement in prediction accuracy, 20.9% improvement in performance and 40% reduction in the number of network contentions.