• DocumentCode
    3697133
  • Title

    Customizable Heterogeneous Acceleration for Tomorrow´s High-Performance Computing

  • Author

    Alessandro Cilardo;José ;Mirko Gagliardi;Rafael T. Gavila

  • Author_Institution
    DIETI, Univ. of Naples Federico II, Naples, Italy
  • fYear
    2015
  • Firstpage
    1181
  • Lastpage
    1185
  • Abstract
    High-performance computing as we know it today is experiencing unprecedented changes, encompassing all levels from technology to use cases. This paper explores the adoption of customizable, deeply heterogeneous manycore systems for future QoS-sensitive and power-efficient high-performance computing. At the heart of the proposed architecture is a NoC-based manycore system embracing medium-end CPUs, GPU-like processors, and reconfigurable hardware regions. The paper discusses the high-level design principles inspiring this innovative architecture as well as the key role that heterogeneous acceleration, ranging from multicore processors and GPUs down to FPGAs, might play for tomorrow´s high-performance computing.
  • Keywords
    "Registers","Computer architecture","Acceleration","Program processors","Hardware","Field programmable gate arrays","Quality of service"
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computing and Communications (HPCC), 2015 IEEE 7th International Symposium on Cyberspace Safety and Security (CSS), 2015 IEEE 12th International Conferen on Embedded Software and Systems (ICESS), 2015 IEEE 17th International Conference on
  • Type

    conf

  • DOI
    10.1109/HPCC-CSS-ICESS.2015.303
  • Filename
    7336329