Scaling analog circuits into deep nanoscale CMOS: Obstacles and ways to overcome them

Analog circuits provide the critical interfaces between the digital world inside today´s integrated circuits and the physical world. Semiconductor technology scaling driven by ‘Moore´s Law’ has resulted in a phenomenal scaling of the performance of digital processors and memory. Continuing design innovations have enabled the scaling of analog interfaces onto scaled CMOS technologies, even though device scaling is a mixed blessing for the analog designer. This paper reviews the scaling challenges for analog circuits ranging from fundamental to practical challenges. Design strategies are outlined that in principle can overcome the challenges and can help guide the search for new circuit paradigms. Several examples of innovative analog design paradigms are reviewed and the opportunities in highly scaled CMOS technologies are outlined.