Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs

Stress equalization and stress removal techniques for mitigating short-term Vth instability issues in SAR ADCs have been experimentally verified using an 80kS/s 10-bit differential SAR ADC fabricated in a 65nm LP CMOS process. The proposed techniques are particularly effective in enhancing the performance of high resolution and low sample rate SAR ADCs which are known to be more susceptible to short-term Vth degradation and recovery effects induced by Bias Temperature Instability (BTI). Experimental data shows that the proposed techniques can reduce the worst case DNL by 0.90 LSB and 0.77 LSB, respectively, compared to a typical SAR ADC.