250-MHz resonator based energy recovery flip-flop for ultra low-power clocking

As eloquent amount of power gets dissipated over the clock network, major attention is required for the clock generation network at the design stage for achieving low power. This work proposes a low power clocking scheme based on energy recovery technique. Differential Conditional Capturing Energy Recovery (DCCER) and Single-ended Conditional Capturing Energy Recovery (SCCER) techniques have been applied over CMOS differential flip-flop and the proposed design shows significant reduction in power and delay values over the conventional architectures. Single phase sinusoidal clock has been used to operate the DFFs. The simulation results show 80% reduction in delay and 78% reduction in power consumption over conventional flip-flops. This design results total power saving of 58% when compared to square wave clocking schemes and flip-flops. Current clock gating solutions are prohibited to apply to the sinusoidal energy recovery clock. In this paper we also have proposed a clock gating solutions which can be able to reduce the power and delay overhead by significant times. A single supply voltage of 1.8V has been used in the total design. Detailed discussion of this low power technique has been done in order to improve the performance at the system level. The design and simulations has been performed in Cadence CMOS 180nm technology.