A high-throughput multi-rate LDPC decoder for error correction of solid-state drives

This paper presents a high-throughput multi-rate low density parity check (LDPC) decoder for error correction in solid-state drives (SSDs). In order to meet the high throughput requirement of SSDs, an adaptive normalized min-sum algorithm (NMSA) is implemented by using multiple look-up tables. With the proposed technique, a reduction in average iteration number of around 22.5%~30.3% is achieved when signal-to-noise ratio (SNR) is 6.14dB, and the area overhead is only 0.87%. The LDPC decoder is implemented in TSMC 65nm standard CMOS technology. For a rate-0.889 length-36864 quasi-cyclic (QC) LDPC code, the decoder achieves a throughput of 14.9 Gb/s with an area of 5.365 mm2, and compares favorably with previously proposed architectures.