Variation-aware core-level redundancy scheme for reliable DSP computation in multi-core systems

Technology scaling, which has enabled high density core integration, also has a detrimental effect on the chip multiprocessor (CMP) reliability due to increasing susceptibility to soft errors. Existing circuit-level and architecture-level fault tolerance techniques often pose large area overheads, and thus more area-efficient solutions are needed. This paper presents a variation-aware system-level design that utilizes the inherent core-redundancy in multi-core DSP systems to form N-Modular Redundant (NMR) sub-systems for error detection and recovery. When soft error rate (SER) variation in the system is present, conventional core-level redundancy system would become ineffective if thread-to-core allocation is not carefully devised. In the proposed scheme, we first analyze the optimal degree of redundancy using mathematical models for a system affected by process variations. Then, a variation-aware thread-to-core mapping algorithm is proposed to optimize system reliability under core resources constraint. The proposed scheme is validated by running the Fast-Fourier Transform (FFT) in a multi-core simulator. The experimental results show that the proposed scheme can achieve an improvement of 2x-3x the reliability metric compared to traditional core-level redundancy methods.