FPGA implementation of an efficient adaptive predistortion algorithm

In modern wireless communication systems, the adaptive digital predistortion (DPD) is widely used to compensate for the nonlinearity in the radio front-end. In the DPD implementation, the conventional coefficient estimation algorithm is computationally intensive and prevents the application of complex DPD models. In [1], we have derived an efficient coefficients estimation algorithm based on orthonormal basis functions that achieves the low computational complexity while maintaining the estimation accuracy. In this paper, we focus on the implementation of this efficient coefficients estimation algorithm on a field programmable gate array (FPGA) platform. Compared with the conventional recursive least squares (RLS) algorithm, the low complexity algorithm can achieve the same linearization performance while saving about 80% hardware resources.