An area efficient real- and complex-valued multiply-accumulate SIMD unit for digital signal processors

This paper explores a real- and complex-valued multiply-accumulate (MAC) functional unit for digital signal processors. MAC units with single-instruction-multiple-data (SIMD) support are often used to increase the processing performance in modern signal processing processors. Compared to a real-valued SIMD-MAC units, the proposed unit uses the same multipliers to also support complex-valued SIMD-MAC and butterfly operations. The area overhead for the complex mode is small. Complex-valued operations speed up signal processing algorithms and make the execution more efficient in terms of power consumption. As a case study, a fast Fourier transform (FFT) is implemented for a VLIW-processor with a complex-valued SIMD butterfly extension. The proposed functional unit is quantitatively evaluated in terms of performance, silicon area, and power consumption.