Highly utilized merge mode estimation for a hardware-based HEVC encoder

High-efficiency video coding (HEVC) is a new video coding standard which offers higher performance than previous video coding standards such as H.264/AVC. Merge mode is one of the new tools adopted in HEVC to improve the inter-frame coding efficiency. Merge mode saves the bits for the motion vector (MV) by sharing the MV with neighboring blocks. Merge mode estimation (MME) is the process of finding a merge mode candidate which achieves the highest compression efficiency. During MME, extensive computations are required due to the motion-compensation and the rate-distortion optimization. In this paper, the characteristics and the computational complexity in the MME process are analyzed. And then, the intrinsic hardware utilization degradation problem is discussed. To improve the utilization of the MME hardware, the hardware efficient MME scheme is proposed. Additionally, the hardware organization which independently performs MMEs for integer motion vector (IMV) and fractional motion vector (FMV) is proposed. Due to the proposed MME and the specially designed hardware organization for that, the MME hardware in this paper achieves high utilization of hardware resources and high throughput of MME processing. The proposed hardware processes 105,474 of 64×64 CTUs per second with a clock frequency of 366 MHz, and its gate counts are 320.6K.