A highly-digitized automotive CAN transceiver in 0.14?m high-voltage SOI CMOS

This paper presents a novel CAN transceiver based on a highly-digitized architecture designed and fabricated in 0.14μm high-voltage SOI CMOS. This advanced BCD process allows the implementation of this innovative architecture which combines digital and high-voltage analog circuits. Hence, the output stage can be split in multiple unit cells successively enabled or disabled by a shift register. It also allows an advantageous implementation of a dual-clock CAN receiver that combines an architecture optimized for high EM Immunity with a low-power mode where a low-frequency clock is used to reduce the power consumption. EMC performance was evaluated according to automotive industry standards. It shows excellent EME and EMI compliance to car manufacturer requirements without using a common-mode choke.