Digital architecture to implement a piecewise-linear approximation for the hyperbolic tangent function

In this paper an 8 bits word-length digital architecture that implements a piecewise-linear approximation for the hyperbolic tangent function is presented. Among the main characteristics of this architecture, it can be highlighted its low memory consumption (only two data breakpoints are considered for function approximation), and its hardware portability because it can be implemented in a wide variety of programmable devices like FPGA, DSP or microcontrollers. In order to verify the feasibility of this proposal, logic circuit simulations in Proteus as well as numerical simulations in Maple, are reported.