An ultra-low-power/high-speed 9-bit adder design: Analysis and comparison Vs. technology from 130nm-LP to UTBB FD-SOI-28nm

A sub-threshold 9-bit adder based on a minority-3 based full adder is designed and analyzed versus technology. A power-delay design space exploration is presented in multiple technology nodes. The performances are demonstrated and compared on spanning technology nodes of 130nm-LP, 65nm-LP-BULK, 28nm-LP-high-k-bulk, 28nm Ultra-Thin-Body-and-BOX (UTFF) FDSOI. An extensive body biasing was then applied to the UTBB FDSOI 28nm technology to adapt the circuit to the target operating frequency of 65MHz. The extensive body biasing exploits the feature provided by the Ultra-Thin-Body-and-BOX Fully Depleted SOI (UTBB FDSOI) technology, which allows a bias range of -300mV ~3V . The design was implemented in physical level, and all the results account for the layout parasitics. A minimum energy point of 1.03f J/(bit.cycle) is achieved in the 28nm-UTFF-FDSOI, at the 0.24V supply with the 1.8MHz operating speed. For the target frequency of 65MHz and a 9-bit adder, a total minimum energy operation of 11f J percycle for a supply voltage of 0.309V and a body voltage of 1.35V is achieved.