• DocumentCode
    3718352
  • Title

    Advanced system in package with fan-out chip on substrate

  • Author

    Yuan-Ting Lin;Brian CC Hsieh;JW Lou;Eatice Chen; Chiyu Wang;Lung Tsai;Adren Hsieh

  • Author_Institution
    Bumping Process Engineering Division, ASE Group Kaohsiung, No. 26, Chin 3rd Road, Nantze Export Processing Zone, Taiwan (R.O.C.) 81170
  • fYear
    2015
  • Firstpage
    273
  • Lastpage
    276
  • Abstract
    In conclusion, FOCoS is successfully developed for advanced SiP. FOCoS is aimed to a large package size and high I/O density (> 1000 I/Os) for high-end application. The existing fan-out and flip-chip techniques provide FOCoS with a short time to market. Moreover, FOCoS has a low cost and thin package potential as compared with 2.5D advanced package by ignoring the interposer. The multi-layers RDL are adopted to interconnect between chip and substrate. The connection on fan-out chip is spreading to a wider pitch through stack via and fine pitch. The challenges of multi-layer RDL and large size fan-out product have been systematic investigated and overcome in new product development stage. Enhanced Ti etching recipe and the PR exposure for optimization are adopted to solve the delamination between PI layers and PR residue issue, respectively. Consequently, FOCoS has passed the product reliability test of TCT700, HAST96 and HTST1000.
  • Keywords
    "Delamination","Substrates","Etching","Packaging","Semiconductor device reliability","Polymers"
  • Publisher
    ieee
  • Conference_Titel
    Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2015 10th International
  • Print_ISBN
    978-1-4673-9690-5
  • Type

    conf

  • DOI
    10.1109/IMPACT.2015.7365240
  • Filename
    7365240