DocumentCode :
3722626
Title :
The Design and Simulation of IIC Communication SOPC Core Based on Avalon Bus
Author :
Hongqiang Ji;Yabin Wang;Xiaofeng Li;Tao Jia
Author_Institution :
Sch. of Mechatron., Beijing Inst. of Technol., Beijing, China
fYear :
2015
Firstpage :
135
Lastpage :
138
Abstract :
In this paper, we designed IIC into adjustable IP (Intelligent Property) core to shorten the develop cycle of IIC interface and improve the reconstruct ability of the system. In SOPC Builder, the hardware design code of IIC was integrated and defined as a port signal type, forming a called IP core. As a result, the development efficiency of the system is enhanced, the reliability of the system become high and the design of the system is less complicated.
Keywords :
"Registers","IP networks","Hardware","Clocks","Mechatronics","Protocols","Writing"
Publisher :
ieee
Conference_Titel :
Computer Science and Mechanical Automation (CSMA), 2015 International Conference on
Type :
conf
DOI :
10.1109/CSMA.2015.33
Filename :
7371637
Link To Document :
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