Title :
OpenTimer: A high-performance timing analysis tool
Author :
Tsung-Wei Huang;Martin D. F. Wong
Author_Institution :
Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, USA
Abstract :
We introduce in this paper, OpenTimer, an open-source timing analysis tool that efficiently supports (1) both block-based and path-based timing propagations, (2) common path pessimism removal (CPPR), and (3) incremental processing. OpenTimer works on industry formats (e.g., .v, .spef, .lib, .sdc) and is designed to be parallel and portable. To further facilitate integration between timing and other electronic design automation (EDA) applications such as timing-driven placement and routing, OpenTimer provides user-friendly application programming interface (API) for inactive analysis. Experimental results on industry benchmarks released from TAU 2015 timing analysis contest have demonstrated remarkable results achieved by OpenTimer, especially in its order-of-magnitude speedup over existing timers.
Keywords :
"Optimization","Logic gates","Clocks","Delays","Pins","Algorithm design and analysis"
Conference_Titel :
Computer-Aided Design (ICCAD), 2015 IEEE/ACM International Conference on
DOI :
10.1109/ICCAD.2015.7372666