New energy recovery logic for ultra low power VLSI applications

This paper presents design of basic gates using a new two phase clocked energy recovery logic. The power dissipation of proposed adiabatic logic inverter comes out to be 30nW, 250nW and 414nW for frequencies 10MHz, 100MHz and 200MHz respectively with a load capacitance of 10fF. Proposed logic saves upto 85% power in comparison to the CMOS logic in the frequency range of 10 to 200MHz. The circuits are implemented using Tanner ECAD tool with 90nm technology.