Time analysis based IOTs (Internet of Things) enable TeraHertz RAM design on 40nm FPGA

This paper subsumes the concept of Internet of Things on a Tera Hertz RAM on the 40nm FPGA. Time analysis has been performed on a Tera Hertz RAM. This produces correspondingly higher speeds as compared to any other form of RAM available. The main focus has been on studying the slack for various frequencies. Slack is a kind of error and should be as low as possible. We aim to find that optimum condition at which the value of slack is minimized. Internet of Things is the core concept used here. It deals with the accession of any device form a fairly large distance. The frequency has been varied between 1GHz and 1THz. The variations in slack, timing score, low pulse slack have been observed. It has been found that the need of the control measures increases at higher frequencies. XILINX 12.1 and Verilog Hardware Description Language have been used for the purpose of analysis. This research would illumine the future of the concept of the Internet of Things and would take up the level of the communication to a step ahead.