GTL based wireless sensor specific energy efficient ALU design on 65nm FPGA

This paper consists of design based on sustainable energy efficient ALU32Bit and for that reason we have used four different members of GTL IO standards on 65nm technology. In this paper, we have considered two main parameters for analysis that are frequencies in GHz and AIRFLOW (LFM 250). We have considered Medium as a default profile for heat sink and environment is constant. Xilinx is used for the simulation of logic with Verilog as hardware description language. We have done our analysis for different frequency values for WLANs based on IEEE 802.11 standards. When we scale down from 60GHz to 0.9 GHz we observed maximum IO power reduction and leakage power reduction in GTL, constant clock power and logic power reduction in all the considered IO standards and maximum Signal power reduction in GTLP_DCI and GTL_DCI.