Title :
A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS
Author :
Woorham Bae;Haram Ju;Kwanseo Park;Sung-Yong Cho;Deog-Kyoon Jeong
Author_Institution :
Inter-University Semiconductor Research Center, Department of Electrical and Computer Engineering, Seoul National University, Seoul, Korea
Abstract :
This paper presents a -245.3 dB FoMJ phase-locked loop based on a ring oscillator and a novel analysis on 2-stage ring oscillator. The proposed PLL generates a 4-phase 10-GHz clock for a 40-Gb/s serial link transmitter. The proposed analysis offers a time-domain insight on 2-stage ring oscillator and a precise prediction on oscillator behavior such as an output frequency and whether the 2-stage ring oscillates or not, based on a simple open-loop approach with a single stage buffer. The prototype chip is fabricated in 65-nm CMOS technology, and the PLL occupies only 0.009 mm2 and dissipates 7.6 mW from 1.2-V supply and 9 mW from 1.3-V supply. The measured integrated jitter of the PLL is 214 fs from 1.2-V supply and 182 fs from 1.3-V supply, which corresponds to -244.6 dB and -245.3 dB FoMJ, respectively.
Keywords :
"Ring oscillators","Phase locked loops","CMOS integrated circuits","Clocks","Inverters","Latches"
Conference_Titel :
Solid-State Circuits Conference (A-SSCC), 2015 IEEE Asian
DOI :
10.1109/ASSCC.2015.7387448